One example of an accelerator control apparatus is described in PTL 1. As illustrated in FIG. 14, the accelerator control apparatus described in PTL 1 includes one master computer 10 and a plurality of slave computers 111 to 113. The master computer 10 includes a data dividing unit 1001 and an overlapping part selection unit 1002. The data dividing unit 1001 divides graphic data in such a way that a graphic data amount included in each divided range is equal. The overlapping part selection unit 1002 selects an overlapping part of processing results received from the respective slave computers 111 to 113 and obtains a total processing result without any overlap. The slave computer 111 includes a graphic processing unit 1111 that processes a divided range. The other slave computers 112 and 113 each also include the same configuration as the slave computer 111.
The accelerator control apparatus of PTL 1 including the configuration operates as follows. The data dividing unit 1001 divides graphic data in such a way as an equal graphic data amount to be included in each divided range. The master computer 10 transmits respective share ranges obtained by combining a divided range and a boundary periphery range of the divided range to the individual slave computers 111 to 113. Graphic processing units 1111 to 1113 of the slave computers 111 to 113 process graphic data received from the master computer 10 independently with each other. The slave computers 111 to 113 transmit the processing results to the mater computer 10. The overlapping part selection unit 1002 makes selection on an overlapping part of the processing results received from the slave computers 111 to 113 and obtains a total processing result without any overlap.